One of the main reasons for the rapid change and growth in information technology (IT) power requirements is the increase in volume of data processed, stored, transmitted, and displayed. As a result, power requirements have grown very rapidly over the last few years. To control the increase in power dissipation due to increased frequency and gate count, operating voltages have been reduced, since power scales linearly with respect to voltage but scales as the square of the frequency. Therefore, the increasing frequency demand forces the voltages down proportionally in order to maintain a reasonable level of power dissipation. Today, feeding this large amount of “ultraclean” current at low voltages with huge transient response capability is the key technology driver of power management for IT.
Such power supply concerns assume particular significance in advanced memory designs currently being implemented. Additionally, rising bus and processing speeds are also demanding newer memory architectures that deliver improved performance by increasing clock frequencies and available bandwidth without pushing up power consumption. To cope with power requirements, industry standard memory modules, e.g., Dual In-line Memory Modules (DIMMS) populated with dynamic random access memory (DRAM) devices, are provided with power supply rails (on a relatively large number of pins) that are powered from system board or main board voltage sources, and are specific to the memory technology. As the performance of the DRAM technology goes up, and timing margins shrink, it is becoming increasingly more difficult for the system board sources to provide tightly regulated power for the DRAM cores as well as input/output (I/O) interface buffers. Furthermore, each generation of DIMM/DRAM technology requires a different power supply which keeps getting lower (e.g., 3.3V, 2.5V, 1.8V, 1.5V and beyond), thereby making it difficult to mix memory technologies on a system board, or provide upgrades to next generation DRAM technology in a cost-effective manner. One skilled in the art will recognize, in addition, that these issues are particularly significant for systems that are deployed in infrastructure with an expected product life of over five years or so since it is difficult to accurately design a system that will be optimized over such a long life span.